Low-complexity multiplierless DCT approximations for low-power HEVC digital IP cores
Image and video compression plays a major role in multimedia transmission. Specifically the discrete cosine transform (DCT) is the key tool employed in a vast variety of compression standards such as H.265/HEVC due to its remarkable energy compaction properties. Rapid growth in digital imaging applications, such as multimedia and automatic surveillance that operates with limited bandwidths has led to extensive development of video processing systems. The main objective of this paper is to discuss some DCT approximations equipped with fast algorithms which require minimum addition operations and zero multipliers or bit-shifting operations leading to significant reductions in chip area and power consumption compared to conventional DCT algorithms. We provide complete design details for several k × k, k = 8, 16 blocked 2-D algorithms for DCT computation with video evaluation using HEVC software encoder. Custom digital architectures are proposed, simulated and implemented on Xilinx FPGAs and verified in conjunction with software models.
Proceedings of the SPIE
Kulasekera, Sunera C.; Madanayake, Habarakada Liyanachchi; Cintra, Renato J.; Bayer, Fabio M.; and Potluri, Uma, "Low-complexity multiplierless DCT approximations for low-power HEVC digital IP cores" (2014). Electrical and Computer Engineering Faculty Research. 4.