Electrical and Computer Engineering Faculty Research


Capacitor Voltage Balancing Using Minimum Loss SVPWM for a Five-Level Diode-Clamped Converter

Document Type

Conference Proceeding

Publication Date

Spring 3-16-2014


DC capacitor voltage imbalance is an inevitable technical concern for the multilevel diode-clamped converters with number of levels higher than two. This paper addresses the balancing of the capacitor voltages based on the capacitor current equalization considering a minimum loss space vector pulse width modulation (MLSVPWM) algorithm for five-level diode-clamped converters. In diode-clamped converter topology, individual capacitors are connected in series on the DC side of the converter. By choosing appropriate switching pattern and their duration in a combined manner, the current passing through each capacitor can be controlled very competently. Using the redundant switching patterns for the proposed control strategy, number of switching that is required for the operation can also be minimized in addition to capacitor voltage balancing, without the requirement of complex calculations. The proposed MLSVPWM modulation technique for voltage balancing is verified using circuit simulations.

Publication Title

29th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)